Most microprocessors, memory chips and related integrated circuits manufactured today are designed with millions of transistors. Therefore, the cost of designing and manufacturing microprocessors, memory chips, and the like is high. In addition, the number of human design errors and manufacturing errors are continually increasing due to added circuit and process complexity. Both the increased number of errors and high cost of manufacturing require that the testing of an integrated circuit be as complete and informative as possible.
In order to improve debugging and testing of an integrated circuit, redundant circuitry is designed into the integrated circuit. The redundant circuitry is usually in the form of small pieces of logic circuitry or circuits known as standard cells. The redundant circuitry is typically NAND gates, inverters, and the like. The redundant circuitry has metal pad input and metal pad output connections that are physically located close to a top passivated surface of the integrated circuit.
A focused ion beam (FIB) machine is commonly used to disconnect a damaged portion of the integrated circuit from the rest of the integrated circuit. Once the damaged portion of the integrated circuit is disconnected, the redundant circuitry is electrically connected by the FIB machine to the rest of the integrated circuit via metal conductors. The added redundant circuitry functionally replaces the damaged circuit in the integrated circuit. Further testing can be performed to further determine errors and functionality without using expensive redesign techniques, new mask formation steps, increased manufacturing, or the like.
The redundant circuitry is usually scattered throughout the integrated circuit and may be rotated to different orientations based on size and space constraints. Therefore, the identification of the redundant cells becomes difficult to ascertain. The difficulty is primarily due to overlying integrated circuit layers obscuring a human user's view of the redundant circuits. In addition, various small and indistinguishable internal features of the redundant circuitry and the fact that redundant circuits are spread throughout the integrated circuit further complicate redundant circuit identification.
Alphanumeric labels have been used to identify test structures which are used for process development and process characterization of an integrated circuit. Alphanumeric numerals are physically large and therefore not available for use in labeling redundant circuitry, which is typically limited by size constraints. In addition, poor visibility of test structures and labels results due to the existance of multiple device layers on an integrated circuit. Topography can also distort or reduce the visibility of circuit features. Therefore, redundant circuit features cannot be relied on to identify specific redundant circuits.